1. Technical Field of the Invention
This disclosure relates to a semiconductor device and more specifically, to a semiconductor device for applying a well bias and a method of fabricating the same.
2. Description of the Related Art
At the present time, advances in VLSI memories leads to considerable power consumption in NMOS devices. Therefore, it is necessary to develop a technology for lowering the power consumption. In view of the necessity, CMOS technology has been suggested. According to the CMOS technology, power is saved at a half to a quarter of the rate of conventional power consumption. A CMOS inverter includes an NMOS transistor and a PMOS transistor. Gates of the NMOS and PMOS transistor constitute an input port of the CMOS inverter, and drains of the NMOS and PMOS transistors constitute an output port of the CMOS inverter. Conventionally, the NMOS transistor is formed within a P-well and the PMOS transistor is formed within an N-well. In general, a power supply voltage (Vdd) is applied to the N-well and a ground voltage (i.e., well bias; Vss) is applied to the P-well. The well bias applied to the P-well and N-well can play a part in enhancing a threshold voltage (Vth) and stabilizing an electric characteristic of each transistor.
A conventional NMOS transistor with a well pick area for applying a well bias is now described below with reference to FIG. 1. A PMOS transistor is similar to the NMOS transistor in construction.
Referring to FIG. 1, a P-well 4 is formed within a substrate 2. Field regions define an active region. An NMOS transistor is formed in the active region between the field regions 8. The NMOS transistor includes a gate stack and a source/drain region 22. The gate stack includes a gate insulating layer 10, a gate electrode 12, and a gate spacer 18. The source/drain region 22 is formed of a lightly doped region 14 and a heavily doped region 20. The source/drain region 22 is positioned in the P-well 4. The P-well 4 is connected to a well pickup region 24 for applying a well bias.
A drain voltage Vds is applied to a drain region of a MOS transistor. A gate voltage Vgs is applied to the gate electrode. A ground voltage Vss is applied to the source region and the well pickup region. In this figure, reference numerals 26a and 26b denote silicide layers that are formed on the gate electrode and the active region, respectively.
However, in the event that a well pickup region is formed at each MOS transistor so as to apply a well bias, a chip area increases. Accordingly, a MOS transistor has been used which has a common well pickup region, as shown in FIG. 2.
Referring to FIG. 2, three NMO transistors TR1, TR2 and TR3 have a common well pickup region 25. In FIG. 2 and FIG. 1, the same numerals denote the same components. Occupying a smaller chip area, the common well pickup region is advantageous to integration. The common well pickup region has no influence upon an NMOS transistor adjacent to the well pickup region. However, the common well pickup region causes an NMOS transistor spaced apart therefrom to be vulnerable to a latch-up phenomenon because the well resistance increases in proportion to the distance between the common well pickup region and the NMOS transistor. The latch-up phenomenon is caused by two parasitic bipolar transistors acting as one thyristor that is turned on abnormally. Due to the latch-up phenomenon, the electrical characteristic of the NMOS transistor may be varied or the MOS transistor may be damaged. In order to prevent the latch-up phenomenon, a well pickup region is advantageously formed next to each MOS transistor. Unfortunately, this increases the area of the chip.
As a result, when a well pickup region is formed in a MOS transistor, the goals of achieving excellent electrical characteristics and reducing a chip area have an inverse relationship.
Embodiments of the invention address these and other limitations in the prior art.